Field of the Invention
The present invention relates to an imaging device and an imaging system.
Description of Related Art
As an example of an imaging device that uses a Time-to-Digital Converter Single-Slope (TDC SS)-type A/D conversion circuit obtained by combining a Time-to-Digital Converter (TDC)-type A/D conversion circuit and a Single-Slope (SS)-type A/D conversion circuit, a configuration disclosed in Japanese Patent Application Publication No. 2011-55196 is known. FIG. 15 illustrates a part of a configuration of a TDC SS-type A/D conversion circuit as a first conventional example. The configuration and an operation of the circuit illustrated in FIG. 15 will be described below.
The circuit illustrated in FIG. 15 has a comparison unit 1031, a latch unit 1033, a counter unit 1034, and a buffer circuit BUF. The comparison unit 1031 has a voltage comparator COMP. An analog signal “Signal” to be A/D-converted and a reference signal Ramp that decreases as time elapses are input to the voltage comparator COMP. The voltage comparator COMP outputs a comparison signal CO based on the result obtained by comparing the analog signal “Signal” to the reference signal Ramp. The latch unit 1033 has a plurality of latch circuits L_0 to L_7. The plurality of latch circuits L_0 to L_7 latch logic states of a plurality of phase signals CK[0] to CK[7] having different phases. The counter unit 1034 has a counter circuit CNT. The counter circuit CNT performs counting on the basis of the phase signal CK[7] output from the latch circuit L_7. A control signal RST is a signal for performing a reset operation of the counter circuit CNT.
The comparison unit 1031 generates a time interval (a size in a time axis direction) according to the amplitude of the analog signal “Signal”. The buffer circuit BUF is an inverting buffer circuit which inverts and then outputs the input signal.
The latch circuits L_0 to L_7 constituting the latch unit 1033 are in an enabled (available, toggled) state when a control signal Hold from the buffer circuit BUF is in an H state (a high state). At this time, the latch circuits L_0 to L_7 output the input phase signals CK[0] to CK[7] without change. In addition, the latch circuits L_0 to L_7 go into a disabled (unavailable, hold) state when the control signal Hold from the buffer circuit BUF transitions from the H state to an L state (a low state). At this time, the latch circuits L_0 to L_7 latch the logic states of the input phase signals CK[0] to CK[7].
Next, the operation of the circuit of the first conventional example will be described. FIG. 16 illustrates waveforms of the reference signal Ramp, the analog signal “Signal”, a start pulse StartP, the phase signals CK[0] to CK[7], the comparison signal CO, the control signal Hold from the buffer circuit BUF, and output signals Q0 to Q7 of the latch circuits L_0 to L_7 of the latch unit 1033. The lateral direction of FIG. 16 represents time, and the longitudinal direction of FIG. 16 represents voltage.
Generation of the phase signals CK[0] to CK[7] is started by a start pulse StartP at a first timing at which the comparison unit 1031 starts comparison. The generated phase signals CK[0] to CK[7] are input to the latch circuits L0 to L7 of the latch unit 1033. Since the control signal Hold from the buffer circuit BUF is in an H state, the latch circuits L0 to L7 are in an enabled state. At this time, the latch circuits L0 to L7 output the phase signals CK[0] to CK[7] without change.
The counter unit 1034 performs counting on the basis of the phase signal CK[7] output from the latch circuit L_7 of the latch unit 1033. In this counting, a count value increases or decreases at a rise or a fall timing of the phase signal CK[7]. The comparison signal CO from the comparison unit 1031 is inverted at a second timing at which a voltage of the analog signal “Signal” substantially matches a voltage of the reference signal Ramp. After the comparison signal CO is buffered by the buffer circuit BUF, the control signal Hold from the buffer circuit BUF goes into an L state at a third timing.
Accordingly, the latch circuits L0 to L7 go into a disabled state. At this time, logic states of the phase signals CK[0] to CK[7] are latched in the latch circuits L0 to L7. The counter unit 1034 causes the count value to be latched as the latch circuit L_7 stops its operation. Digital data corresponding to the analog signal “Signal” is obtained based on the logic states latched by the latch unit 1033 and the count value latched by the counter unit 1034.
As another example of an imaging device using a TDC SS-type A/D conversion circuit, the configuration disclosed in Japanese Patent Application Publication No. 2012-39386 has been proposed. FIG. 17 illustrates a part of a configuration of a TDC SS-type A/D conversion circuit of a second conventional example. The configuration and operation of the circuit illustrated in FIG. 17 will be described below.
The circuit illustrated in FIG. 17 has a comparison unit 1031, a latch control unit 1032, a latch unit 1033, and a counter unit 1034. The comparison unit 1031 and the counter unit 1034 are the same as the comparison unit 1031 and the counter unit 1034 illustrated in FIG. 15 respectively.
The latch control unit 1032 has an inversion delay circuit DLY and an AND circuit AND1. The latch control unit 1032 generates a control signal for controlling an operation of the latch unit 1033. The inversion delay circuit DLY receives an input of a comparison signal CO from the comparison unit 1031. The inversion delay circuit DLY generates a delay comparison signal xCO_D by inverting and delaying the comparison signal CO. The AND circuit AND1 receives the delay comparison signal xCO_D from the inversion delay circuit DLY and the comparison signal CO from the comparison unit 1031. The AND circuit AND1 outputs a control signal Hold_L having the logical product (AND) of the delay comparison signal xCO_D and the comparison signal CO.
The latch unit 1033 has latch circuits L_0 to L_7 and an AND circuit AND2. The latch circuits L_0 to L_7 are the same as the latch circuits L_0 to L_7 illustrated in FIG. 15. The AND circuit AND2 outputs a control signal Hold_C having the logical product (AND) of the delay comparison signal xCO_D from the inversion delay circuit DLY of the latch control unit 1032 and a control signal Enable to the latch circuit L_7.
Next, the operation of the circuit of the second conventional example will be described. FIG. 18 illustrates waveforms of a start pulse StartP, phase signals CK[0] to CK[7], the delay comparison signal xCO_D, the comparison signal CO, the control signal Hold_L from the AND circuit AND1, the control signal Enable, the control signal Hold_C from the AND circuit AND2, and output signals Q0 to Q7 of the latch circuits L_0 to L_7 of the latch unit 1033. The lateral direction of FIG. 18 represents time, and the longitudinal direction of FIG. 18 represents voltage.
Differences from the operation of the circuit of the first conventional example will be described below. After a first timing at which the comparison unit 1031 starts comparison, the comparison signal CO from the comparison unit 1031 is in an L state until voltages of an analog signal “Signal” and a reference signal Ramp input to the comparison unit 1031 substantially match each other. While the comparison signal CO is in the L state, the delay comparison signal xCO_D from the inversion delay circuit DLY is in an H state. Since the delay comparison signal xCO_D from the inversion delay circuit DLY is in the H state and the comparison signal CO from the comparison unit 1031 is in the L state, the control signal Hold_L from the AND circuit AND1 is in the L state. Thus, the latch circuits L_0 to L_6 are in a disabled state.
On the other hand, since the control signal Enable is in an H state at the first timing at which the comparison unit 1031 starts comparison, and the delay comparison signal xCO_D from the inversion delay circuit DLY is in the H state, the control signal Hold_C from the AND circuit AND2 is in an H state. Thus, the latch circuit L_7 is in an enabled state.
Subsequently, the comparison signal CO from the comparison unit 1031 is inverted at the second timing at which the voltage of the analog signal “Signal” matches the voltage of the reference signal Ramp. Since the delay comparison signal xCO_D from the inversion delay circuit DLY is in the H state and the comparison signal CO from the comparison unit 1031 changes from the L state to the H state, the control signal Hold_L of the AND circuit AND1 changes from the L state to the H state. Accordingly, the latch circuits L_0 to L_6 go into an enabled state.
Furthermore, the delay comparison signal xCO_D from the inversion delay circuit DLY changes from the H state to the L state at a third timing that arrives after a predetermined period of time elapses from the inversion of the comparison signal CO from the comparison unit 1031. Thus, since the control signal Hold_L of the AND circuit AND1 and the control signal Hold_C of the AND circuit AND2 change from an H state to an L state, the latch circuits L0 to L7 go into disabled states.
In the above-described operation, the latch circuits L_0 to L_6 operate only in the period from the second timing to the third timing. Therefore, compared with in the first conventional example, a current consumption can be reduced.
As a specific configuration of the inversion delay circuit DLY, a configuration to which a so-called delay line in which a number of inverter circuits are connected is applied may be conceived. The delay line is disclosed in, for example, ITE Technical Report Vol. 37, No. 29.